1. Field of the Invention
The present invention relates to an SOI (Semiconductor On Insulator) type thin-film transistor, and more particularly to a technique for fixing a potential of its body (referred to as xe2x80x9cbody potentialxe2x80x9d hereinafter).
2. Description of the Background Art
FIG. 18 is a cross-sectional view illustrating a structure of a general SOI type thin-film transistor 900. The thin-film transistor 900 is formed as an n-channel MOS transistor in a semiconductor layer 902 provided on an insulator 901. The insulator 901 may be formed as a buried layer in a not-shown semiconductor substrate.
In the pxe2x88x92 type semiconductor layer 902, a source region 903 and a drain region 904 both of which are n+ type semiconductor layers are provided at a distance from each other. The semiconductor layer 902 sandwiched by the source region 903 and the drain region 904 is termed xe2x80x9cbodyxe2x80x9d of the thin-film transistor 900. Above the body, a gate electrode 907 made of e.g., polysilicon is provided with a gate insulating film 906 interposed therebetween.
Since the semiconductor layer 902 is provided on the insulator 901, its body potential is in a floating state in the structure of FIG. 18. In this state, there are possibilities of generation of leak current and unstable operation of the thin-film transistor 900 due to variations in power-supply level and ground level and parasitic bipolar effect. The parasitic bipolar effect here refers simply to a phenomenon that positive holes created by impact ionization are accumulated in the body and the body potential thereby rises to increase a leak current in the thin-film transistor 900 as an n-channel MOS transistor.
There may be a case where a cosmic ray such as an a ray enters the body to form a pair of an electron and a positive hole. Since the thin-film transistor 900 is used in a state where a channel is formed by inverting a surface of the body into n type, the positive hole is accumulated, though the electron is drawn out, to raise a possibility of inviting a rise of body potential.
To solve the above problem, a technique for fixing the body potential has been proposed. FIG. 19 is a cross-sectional view of a first technique in the prior art, illustrating a structure of a thin-film transistor 800 and a structure for fixing its body potential. The thin-film transistor 800 comprises a pxe2x88x92 type semiconductor layer 802 as a body formed on an insulator 801 and a source region 803 and a drain region 804 both of which are of n+ type and provided thereabove. Above the body, a gate electrode 807 is provided with a gate insulating film 806 interposed therebetween.
Alongside the thin-film transistor 800, an isolation oxide film 809 is formed by LOCOS oxidization of the semiconductor layer 802. Below the isolation oxide film 809, above the insulator 801, a region 805a is formed by enhancing the conductivity of the semiconductor layer 802. On the opposite side of the thin-film transistor 800 with respect to the isolation oxide film 809, a p type region 805b and a p+ type region 805c are layered on the insulator 801 in this order. The regions 805a, 805b and 805c adjoin the semiconductor layer 802 in this order, and when a potential VB is applied to the region 805c, the body potential can be fixed at a position away from the thin-film transistor 800 with the isolation region 809 interposed.
Since the first background-art technique, however, uses the isolation oxide film 809, it is not suitable for integration. Further, a structure much like that of FIG. 19, where the p type semiconductor layer is provided between the source region and the insulator to draw the positive hole, is disclosed in, for example, Japanese Patent Application Laid Open Gazette No. 6-232405.
On the other hand, the thin-film transistor is often used with the potential applied to the source region (referred to simply as xe2x80x9csource potentialxe2x80x9d) and the body potential being equal, and on the premise of such a use, a structure for fixing the body potential can be formed locally in the source region. FIG. 20 is a plan view illustrating a structure of a thin-film transistor 700 that is advantageous from this viewpoint. The second technique in the background art is disclosed in, for example, xe2x80x9cSilicon-on-insulator technology: materials to VLSIxe2x80x9d by J. P. Colinge (Kluwer Academic Publishers, 2nd Ed.).
With the gate electrode 707 centered, on the left hand of this figure provided are an n+ type source region 703 and p+ type body-potential drawing regions 705a and 705b which sandwich the region 703 vertically in this figure, and on the right hand of this figure provided is a drain region 704. A contact structure for supplying the body potential and the source potential is formed at a contact region 310 provided covering part of the body-potential drawing regions 705a and 705b across the source region 703. This structure eliminates the necessity of the LOCOS oxide film used in the first background-art technique, thereby being suitable for integration.
The second background-art technique, however, has great problems as follows. The first problem is due to the position of the body-potential drawing region 705a. The body is provided in the back of the gate electrode 707 in this figure, though not shown, and a channel is formed mainly in a portion surrounded by the source region 703, the drain region 704 and the gate electrode 707. From this portion, the positive hole should be drawn.
In the structure of FIG. 20, the body-potential drawing regions 705a and 705b are positioned at an end of the source region 703 along a direction where the gate electrode 707 extends (in a vertical direction of this figure). Therefore, in order to effectively draw the positive hole from the body, a pair of body-potential drawing regions 705a and 705b are needed. For example, if the body-potential drawing region 705a is not provided, the body-potential drawing region 705b can not effectively draw the positive hole from a portion on the upper side of this figure in the body. This needs a larger area for the body-potential drawing regions 705a and 705b, and a portion which does not function as a channel in a direction (gate width) where the gate electrode 707 extends increases in width. That inhibits integration of the thin-film transistor.
The second problem becomes pronounced in a case where the gate electrode 707 is made of polysilicon and the like. Impurity implantations for forming the source region and the drain region are performed, in general, by using the gate electrode and the gate insulating film provided between the gate electrode and the body as a mask in a self-aligned manner. When an impurity to be implanted into the polysilicon to enhance the conductivity as the gate electrode is equivalent in conductivity to those for the source region and the drain region, the conductivity of the gate electrode is obtained by impurity implantation for forming the source region and the drain region.
If a p type impurity is implanted to also form the p+ type body-potential drawing regions 705a and 705b of FIG. 20 in a self-aligned manner, however, an effect of the n type impurity which the gate electrode 707 has is counter-doped. The gate electrode 707 comprises a straight portion 707b which is straight in a direction where the gate electrode 707 extends and a contact portion 707a in which a contact structure is formed to apply a predetermined electrical signal to the gate electrode. The conductivity is degraded in portions 401a and 401b of the straight portion 707b near the p+ type body-potential drawing regions 705a and 705b at an end (on the left hand of FIG. 20) in a direction (horizontal direction of this figure) orthogonal to the direction where the straight portion 707b extends. This phenomenon becomes especially pronounced in the portion 401b near the contact portion 707b because transmission of signals to the straight portion 707b is degraded.
Even if a mask is used to selectively implant the p type impurity to form the p+ type body-potential drawing regions 705a and 705b out of the self-aligned manner, a margin for alignment of the mask is needed in order to surely bring the body-potential drawing regions 705a and 705b into contact with the body, and implantation of the p type impurity into the gate electrode 707 can not be virtually avoided.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: an insulator; a first semiconductor layer of a first conductivity type, having a first main surface adjacent to the insulator and a second main surface on the opposite side to the first main surface; an insulating layer provided on the second main surface; a control electrode provided on the insulating layer extending in a first direction, immediately below which the first semiconductor layer is divided into first and second regions along a second direction orthogonal to the first direction; a second semiconductor layer of a second conductivity type opposite to the first conductivity type provided in the first region; and a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer of the first conductivity type, the second conductivity type and the first conductivity type, respectively, provided in the second region extending from the second main surface to the first main surface and exposed in this order on the second main surface along a side end of the control electrode on a side of the first region.
Preferably, the third, fourth and fifth semiconductor layers have the same length along the second direction.
Preferably, the length of the fourth semiconductor layer along the second direction is shorter than those of the third and fifth semiconductor layers along the second direction.
Preferably, the third semiconductor layer and the fifth semiconductor layer are connected farther away from the control electrode than an end portion of the fourth semiconductor layer away from the control electrode.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the control electrode has a straight portion extending in the first direction; and a wide portion widened in the second direction at a position of the fourth semiconductor layer in the first direction.
Preferably, the length of the fourth semiconductor layer along the second direction is shorter than those of the third and fifth semiconductor layers in the second direction.
Preferably, the third semiconductor layer and the fifth semiconductor layer are connected farther away from the control electrode than an end portion of the fourth semiconductor layer away from the control electrode.
According to a third aspect of the present invention, the semiconductor device comprises: a pair of semiconductor elements each including an insulator; a first semiconductor layer of a first conductivity type, having a first main surface adjacent to the insulator and a second main surface on the opposite side to the first main surface; an insulating layer provided on the second main surface; a control electrode provided on the insulating layer extending in a first direction, immediately below which the first semiconductor layer is divide into first and second regions along a second direction orthogonal to the first direction, and having a straight portion extending in the first direction and a wide portion widened in the second direction at a position of the fourth semiconductor layer in the first direction; a second semiconductor layer of a second conductivity type opposite to the first conductivity type provided in the first region; and a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer of the first conductivity type, the second conductivity type and the first conductivity type, respectively, provided in the second region extending from the second main surface to the first main surface and exposed in this order on the second main surface along a side end of the control electrode on a side of the first region, and a pair of the wide portions being widened in opposite directions to each other.
Preferably, the pair of wide portions are widened in such directions as to go away from a boundary between the pair of semiconductor elements.
Preferably, the third semiconductor layer and the fifth semiconductor layer are connected farther away from the control electrode than an end portion of the fourth semiconductor layer away from the control electrode.
The present invention is also directed to a method of manufacturing a semiconductor device. According to a fourth aspect of the present invention, the method comprises the steps of: (a) forming a first semiconductor layer of a first conductivity type on an insulator, which has a first main surface adjacent to the insulator and a second main surface on the opposite side to the first main surface; (b) forming a first insulating layer on the second main surface of the first semiconductor layer; (c) forming a first control electrode having a straight portion provided on the first insulating layer extending in a first direction and a wide portion extending from the straight portion along a second direction opposite to the first direction; (d) introducing a first impurity of the first conductivity type into the first semiconductor layer using at least an end of the wide portion of the first control electrode as a mask to form a second semiconductor layer; and (e) introducing a second impurity of a second conductivity type opposite to the first conductivity type into the first semiconductor layer using the first control electrode and a shield covering the second semiconductor layer as masks to form a third semiconductor layer and a fourth semiconductor layer of the second conductivity type sandwiching the first semiconductor layer below the straight portion.
According to a fifth aspect of the present invention, in the method of the fourth aspect, the step (a) has the step of forming a fifth semiconductor layer of the second conductivity type, which has a first main surface adjacent to the insulator and a second main surface on the opposite side to the first main surface thereof and is adjacent to the first semiconductor layer with a boundary therebetween, the step (b) has the step of forming a second insulating layer on the second main surface of the fifth semiconductor layer, the step (c) has the step of forming a second control electrode which has a straight portion provided on the second insulating layer extending in the first direction and a wide portion extending from the straight portion along the second direction, the first impurity is introduced in the step (d) using a first shield covering a position at a predetermined distance or more from an end of the wide portion of the first control electrode, a range from the straight portion of the first control electrode to the boundary and a range within a predetermined distance from an end of the wide portion of the second control electrode, the second impurity is introduced in the step (e) using a second shield covering a position at a predetermined distance or more from the end of the wide portion of the second control electrode, a range from the straight portion of the second control electrode to the boundary and a range within a predetermined distance from the end of the wide portion of the first control electrode, the method further comprising the steps of: (f) introducing a third impurity of the first conductivity type using a third shield having the same pattern as the first shield before the steps (d) and (e); and (g) introducing a fourth impurity of the second conductivity type using a fourth shield having the same pattern as the second shield before the steps (d) and (e).
Preferably, the wide portion of the first control electrode and the wide portion of the second control electrode are extended in opposite directions.
Preferably, both the first control electrode and the second control electrode are widened in such directions as to go away from the boundary.
In the semiconductor device of the first aspect of the present invention, since the fourth semiconductor layer is provided over the whole thickness of the first semiconductor layer, the potential of the first semiconductor layer, i.e., the body potential can be fixed by the fourth semiconductor layer. Since the fourth semiconductor layer is sandwiched between the third and fifth semiconductor layers along the direction where the control electrode extends, drawing of carries associated with fixing of the body potential can be performed more effectively from the first semiconductor layer between the second and third semiconductor layers and from the first semiconductor layer between the second and fifth semiconductor layers, as compared with a case where the fourth semiconductor layer is positioned at an end portion in the direction where the control electrode extends, and does not require a large area of the fourth semiconductor layer. Furthermore, since the third, fourth and fifth semiconductor layers are formed over the whole thickness of the first semiconductor layer, it is possible to suppress an effect of a pn junction, e.g., parasite of junction capacitance.
In the semiconductor device of the second aspect of the present invention, since the conductivity of the straight portion is hard to deteriorate even if the conductivity of the wide portion in the control electrode positioned near the fourth semiconductor layer is deteriorated, it is possible to avoid deterioration of function of the control electrode.
In the semiconductor device of the third aspect and the method of manufacturing a semiconductor device of the sixth aspect of the present invention, wiring of a power-supply line can be easily performed when an inverter is constituted of a pair of semiconductor devices.
In the method of manufacturing a semiconductor device of the fourth aspect of the present invention, since the first impurity is introduced into the first semiconductor layer by using the wide portion as a mask in the step (d), it is possible to avoid introduction of the first impurity into the straight portion when the second semiconductor layer which is adopted as a region for drawing the body potential is formed. Therefore, the conductivity of the straight portion is not deteriorated. Further, since introduction of the second impurity into the second semiconductor layer is suppressed in the step (e), the conductivity of a region for drawing the body potential is not deteriorated.
In the method of manufacturing a semiconductor device of the fifth aspect of the present invention, since the first and third shields have the same pattern and the second and fourth shields have the same pattern, the LDD structure can be obtained while the photomask is diverted.
An object of the present invention is to provide a new structure for drawing the body potential of the SOI type thin-film transistor and a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.